Modified PS design

[johnsonad]

I'm working on a modified PS in PSUD for a build.  I'm barely a novice but can punch in the numbers and thought others might like to see this so far. 

It will be a voltage doubler CLCLC design but I'm unsure if my results are good.  Any input would be greatly appreciated.

There are two photos, one with an electrolytic second stage and a second with a film cap second stage of a lower value. 

[Paul Birkeland]

Try simulating for 10,000ms.

You can zoom out on your voltage line, then use the cursor to kind of draw a zoom box around it.  Eventually, it will give you a sufficient zoom level to see the amount of ripple.

[johnsonad]

Something like this?  Where the voltage stabilizes?  If not, where should I be zooming in on?

[Paul Birkeland]

Yeah, now you can zoom in on the line on the right end where it flattens out.

[johnsonad]

Got it!  Here is the design with electrolytics in the second stage and 100uF final at 3,000ms.  I can't see any ripple.  Is this zoomed in enough?

[Paul Birkeland]

Keep zooming in until you see the ripple.  (Remember, 3mV of ripple is 0.003V, so you may have to zoom way in)

[johnsonad]

Got it though I'm not sure how to measure how much ripple that is.....

[Paul Birkeland]

Less than 1mV.

[johnsonad]

I'm assuming that's a good thing With it that low, should I change the design to optimize for rise response or anything else or is the ripple the key goal?

[Paul Birkeland]

I'm assuming that's a good thing With it that low, should I change the design to optimize for rise response or anything else or is the ripple the key goal?

Rise response?

For ripple - model the Paramount power supply, look at the power supply ripple, then compare that to what you have.

[johnsonad]

I just ran the sim and wow, that is a difference.....  Thank you for recommending the design.

Rise response, I must be speaking out of terms.  I understand it as the time it take to achieve output voltage.  The shape and speed of the voltage rise. Does this have an real bearing on the design or should I focus strictly on the ripple?

[Paul Birkeland]

Rise response, I must be speaking out of terms.  I understand it as the time it take to achieve output voltage.  The shape and speed of the voltage rise. Does this have an real bearing on the design or should I focus strictly on the ripple?

The simulation is pretty limited, it assumes that you have a load on the power supply the instant you flick the switch, which you do not.  You can try a stepped load simulation, try 5mA of current for 5 seconds, then full current.  You may see a decent spike in the DC voltage during startup, though this is not anything to be particularly worried about.

[johnsonad]

Thanks Paul.  I don't see any real difference with the stepped response.

Should I consider lowering the value of the last capacitor?

[Paul Birkeland]

What's your target operating point again? (we'll just compile it in this thread for reference) 

To some degree, the extra LC stage may be of no benefit.

[johnsonad]

I'm going to try the 350v, 50mA, 5k OP to start.  Here is the ripple with the last LC stage removed. The voltage is up 17v or so.